1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a wiring or interconnection structure of the semiconductor device.
2. Description of the Prior Art
FIG. 1 and FIG. 2 are sectional views of a conventional semiconductor device. In FIG. 1, metallic upper wiring layers 105 are depicted to be perpendicular to the figure space. In FIG. 2, metallic lower wiring layers 102 are depicted to be perpendicular to the figure space.
According to the prior art, as shown in FIG. 1 and FIG. 2, contact holes or through holes are connected to adjacent wiring layers so that multilayer interconnections of the semiconductor device are constructed. Then it is required that wiring layers are set thick to leave margins in matching by lithography where the contact or through holes are connected to the wiring layers.
In FIG. 1 and FIG. 2, a numeral 101 represents a substrate structure including wiring layers or elements, a numeral 102 metallic lower wiring layers or a structure including elements, a numeral 103 an inter-layer insulating film, a numeral 104 contact holes or through holes (the contact holes are used when the ground layer includes elements whereas the through holes are used when the ground layer includes metallic wiring), a numeral 105 metallic upper wiring layers, and a numeral 106 an inter-layer insulating film or a passivation film.
FIG. 3 shows positioning of the contact or through holes 104 and each wiring layer.
As shown in FIG. 4, recent semiconductor devices are provided with a high density wiring structure called a borderless structure in which the diameter of each of the contact or through holes 204 is set equal to a width of the metallic lower (or upper) wiring layer 202.
However, as shown in FIG. 1, the wiring layers are set larger in width at the contact areas with the contact or through holes to leave margins in matching by the photolithography. Accordingly, a pitch between the wiring layers is essentially decided by an interval between the wiring layers at the contact areas of the contact or through holes and the upper or lower layers. The width of the wiring layers is decided not only by design rules but also by an efficiency of steppers and flatness of a device accomplished by the photolithography, etc. As for a conventional device, there is left a margin of 0.2 to 0.3 micron on one side of each wiring layer. It is implied that a width of each wiring layer as broadened by 0.4 to 1.0 micron on both sides. Accordingly, the device is highly integrated, and requires a superficial width of the wiring layers broadened by the above values as compared to an actual width of the wiring layers, which causes an obstacle to realize a high density.
In more detail, as shown in FIG. 5, when the contact or through holes 304 are arrayed to be aligned with each other in a single line margins in matching the contact or through holes 304 and each layer decide the minimum interval between the wiring layers. Realization of high density requires, as shown In FIG. 6, that the contact or through holes 308 connected to adjacent wiring layers 306 should be arrayed alternately without being aligned in a single line with each other, which restricts a layout of the contact or through holes 308 connected to adjacent wiring layers 306. Furthermore, as shown in FIG. 6, a high density can not be realized, because a pitch between the wiring layers requires at least a margin in matching on one side of each wiring layer.
As shown in FIG. 4, it is possible to realize a high density of the wiring pitch without leaving margins in matching by the photolithography, when the borderless structure, instead of the margin, is employed and a diameter of each contact or through hole is set equal to a width of each wiring layer. In practical manufacturing, when a misalignment of masks in the photolithography occurs, contact areas of the contact or through holes and the wiring layers decrease, which reduces the reliability of wire-connections, that is, allowable current density. In conclusion, there is a disadvantage not to sufficiently realize a high density structure without deciding a pitch between the wiring layers taking into account the misalignment of masks.